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NTE797 Integrated Circuit TV Chroma Processor
Features; D Phase-Locked Subcarrier Regeneration Utilizes Sample-And-Hold Techniques D Automatic Chrominance Control (ACC)/Killer Detector Employs Sample-And-Hold Techniques D Supplementary ACC with an Overload Detector to Prevent Oversaturation of this Picture Tube D Sinusoidal Subcarrier Output D Keyed Chroma Output D Emitter-Follower Buffered Outputs for Low Output Impedance D Linear DC Saturation Control Absolute Maximum Ratings: (TA = +25C unless otherwise specified) Device Dissipation (TA +55C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750mW Derate Linearly Above TA = +55C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.9mW/C DC Supply Voltage (Across Pin5 and Pin12, Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2V DC Current: Into Pin12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38mA Into Pin14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA DC Voltage (Pin9) Negative Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5V Positive Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V Operating Ambient Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to +85C Storage Temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150C Lead Temperature (During Soldering, 1/32 in (0.79mm) from case, 10sec max.), TL . . . . . . +265C Note 1. This rating does not apply when using the internal zener reference in conjunction with an external pass transistor.
Electrical Characteristics: (TA = +25C, chroma control at maximum position for all characteristics test except for chroma output test. For this test, control should be set at minimum position.)
Characteristic Static Characteristics Voltage Regulator Supply Current Dynamic Characteristics (Note 2) Pull-In Range (Note 3) Oscillator Output 100% Chroma Output Overload Detector Minimum Chroma Output 200% Chroma Output 20% Chroma Output Kill Level V8 V8 V15 V15 V15 V15 V15 VTP1 Note 3 2 1 1 1 1 1 1 2 2 2 1 2 2 2 2 0.5Vp-p 0 0.5Vp-p 0.5Vp-p 0.5Vp-p 1Vp-p 0.1Vp-p vary 250 0.6 1.4 0.4 - 70 40 5 - 1.0 2.7 - - 100 - - - - - 0.7 20 140 105 60 Hz Vp-p Vp-p Vp-p mVp-p % of 100% reading mVp-p V12 2 2 0 10.1 11.2 12.1 V Test Measurement & Symbol Switch S1 Pos. S2 Chroma Input TP1 Min Typ Max Unit
Note 2. Except for pull-in range testing, tune oscillator trimmer capacitor for free-running frequency of 3.579545 MHz 10Hz. Note 3. Set Switch 1 to Position 2, detune oscillator 250Hz, set Switch to Position 1, and check for oscillator pull-in. Circuit Description: The chroma input is applied to Pin1 through the desired band-shaping network. A 2,450-ohm resistor should be placed in series with Pin1 to minimize oscillator pickup in the first chroma amplifier. This amplifier supplies signals to the second chroma amplifier and to the ACC and AFPC detectors. The first chroma amplifier is gain-controlled by the ACC amplifier. A horizontal keying pulse is applied to Pin9. This pulse must be present to ensure proper operation of the oscillator circuit. The subcarrier burst is sampled during the keying interval in the AFPC detector. The error voltage, produced at Pin2 and proportional to the burst phase, is compared to the quiescent bias voltage at Pin3 by the sample- and-hold circuitry. This "compared" voltage controls the phase-shifting network in the phase-locked loop. The operation of the AFPC loop is independent of any external adjustments or voltages except for an initial capacitor adjustment to set the free-running frequency. The regenerated oscillator signal at Pin8 is applied internally to the AFPC and ACC detectors through +45 - and -45 -degree phase- shifter networks to establish the proper phase relationship for these detectors. The ACC detectors, which also samples the burst during the keying interval, produces a correction voltage proportional to the burst amplitude. The correction voltage is compared to the quiescent bias level using sample- and-hold circuitry similar to that used in the AFPC portion of the circuit. The "compared" voltage is applied internally to the ACC amplifier and killer amplifier. Because the amplifier gains and killer threhold are determined by the ratios of the internal resistors, these functions are independent of external voltages or controls. The attenuated chroma signal is fed to the second chroma amplifier, where the burst is removed by keyer action. The killer amplifier, the chroma gain control, and the overload detector control the action of the second chroma amplifier, whose gain is proportional to the DC voltage at Pin16. The overload detector (Pin13) receives a sample of the chroma output (Pin15) and detects the peak of the signal. The detected voltage is stored in an external capacitor connected to Pin16. This stored voltage on Pin16 affects the gain of the second chroma in the same manner as the chroma gain control.
Pin Connection Diagram
Chroma Input AF PC Filter Network Bypass RF Bypass GND Crystal Filter Crystal Filter Carrier Output
1 2 3 4 5 6 7 8
16 Chroma Gain Control 15 Chroma Output 14 Zener Reference 13 Overload Det 12 VCC 11 ACC Filter Network 10 ACC Filter Network 9 Horiz Keying Input
16
9 .260 (6.6) Max
1
8
.850 (21.6)
.180 (4.0)
.100 (2.54)

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